muffassir wrote on Dec 15th, 2011, 12:31am:Here is the paper by P.Hasler...
on FGMOS..
What u mean by bias curves...I have simulated the single FGMOS for dc analysis..Do you mean Id vs Vds curves..
That is anotheer way of describing a bias curve, yes, where are all of your transistors on their respective bias curves?
As for the paper, this is a research paper that does not give
reliability and retain-ability of the method.
Claims are based on somebody else's work:
"4uV over a 10 year period"
Show me real data for this, it might be in the other paper, but I doubt it.
Also, comments like using resistance values in simulation of 10E26 ohms
also raises red flags.
(that's simulator nonsense not real silicon)
Better credibility if in IEEE JSSC or IEEE EDS - not Database Symposium paper.
One EDS paper cited, but thats it.
I would not use the technique in anything that had to work reliaably