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muffassir Junior Member Offline Posts: 13 Planet Earth	Re: 4-quad current multiplier Reply #30 - Dec 15^th, 2011, 12:22am Hi all , Here is the Paper on the Multiplier ...Please see both the attchments .The previous and this one..
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muffassir Junior Member Offline Posts: 13 Planet Earth	Re: 4-quad current multiplier Reply #31 - Dec 15^th, 2011, 12:31am Here is the paper by P.Hasler... on FGMOS.. What u mean by bias curves...I have simulated the single FGMOS for dc analysis..Do you mean Id vs Vds curves..
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RobG

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Bozeman, MT

Re: 4-quad current multiplier
Reply #32 - Dec 15^th, 2011, 6:49am

loose-electron wrote on Dec 14^th, 2011, 4:36pm:

RobG wrote on Dec 14^th, 2011, 12:41pm:

loose-electron wrote on Dec 14^th, 2011, 11:36am:

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

They use tunneling to put the proper amount of charge on the gate. In theory this will never leak off so it will maintain. The floating cap pretty much acts like a battery in series with the gate. I've seen circuits published where the idea is used to trim opamp offsets or even provide voltage references. I (and others) have a hard time believing that the charge will remain constant over long periods of time, especially for commercial products that can't fail in the field after a year, but Hassler and others swear it will.

They may swear by it, but the rest of the world will swear at it.

Yeah, I'm not ready to use it for analog. Sometimes it fails for digital! I did see a FG voltage reference in JSSC a few years ago and was hoping better information would come out on the long term stability of the method. It would be a great way to build a reference if stable.

Here are some more references from the red rag:
http://scholar.google.com/scholar?as_q=floating+gate&num=10&btnG=Search+Scholar&...

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loose-electron

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Re: 4-quad current multiplier
Reply #33 - Dec 15^th, 2011, 8:16pm

muffassir wrote on Dec 15^th, 2011, 12:31am:

Here is the paper by P.Hasler...
on FGMOS..

What u mean by bias curves...I have simulated the single FGMOS for dc analysis..Do you mean Id vs Vds curves..

That is anotheer way of describing a bias curve, yes, where are all of your transistors on their respective bias curves?

As for the paper, this is a research paper that does not give
reliability and retain-ability of the method.

Claims are based on somebody else's work:
"4uV over a 10 year period"

Show me real data for this, it might be in the other paper, but I doubt it.
Also, comments like using resistance values in simulation of 10E26 ohms
also raises red flags.

(that's simulator nonsense not real silicon)

Better credibility if in IEEE JSSC or IEEE EDS - not Database Symposium paper.
One EDS paper cited, but thats it.

I would not use the technique in anything that had to work reliaably

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Jerry Twomey
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