I'm trying to find an answer on a rather general question that in my case showed up as a consequence of oscillation during start-up in an op-amp connected as a buffer:

- The input of my buffer goes connected to a voltage reference that overshoots while I'm ramping the power supply (say 5us ramp from 0-5v). A few us after the power supply voltage reaches 5v,  the reference also settles
- The buffer shows an oscillation somewhere during the power supply ramp, such oscillation is sustained even when the input overshoot is gone and the average output value is equal to the input reference voltage.

I obviously checked the stability conditions around the operating point and the loop is by far stable. I also tried checking different op-points through which the buffer goes during power supply ramp but all of them are showing the loop is stable. It is clear I'm not finding the sweet spot at which the loop is not stable, but then the question arose:

Can a negative feedback loop that goes from a non-stable operating point - at which it oscillates - to a stable one and keep the oscillatory condition? The answer seems to be yes but it is not clear to me how that can happen.

I'm looking forward to see what you opinion is on this.
Thanks

Tosei

hello chooper,
yes, any -ve feedback will get you the stable operating point after some disturbance. did you check the with proper loadings about stability? Because some times breaking at wrong place or considering wrong loading gives you wired results..so please post schematic and oscillation waveforms...

Thanks,
Raj.

buddypoor wrote on Jan 12^th, 2012, 11:28am:


Hi Buddypoor,

thanks for answering...I knew you were going to be interested on this one  :). My answers

1) These are only simulation based results.
2) The schematic is no handy now (I could post it later) but yes, it is a simple unity gain configuration
3) The topology is a folded cascode, PMOS input diff pair one stage amp with a follower on the output to provide current capability

Best
Tosei

Vladislav D wrote on Jan 12^th, 2012, 11:44am:


Hi Vladislav,

That's a good tip and I need to check them. The oscillation is around few MHz and about hundred mv or so. So I guess there is a chance that might be the case.
Anyway, I think I would need the biasing currents oscillating all the time to keep the oscillation on the buffer amplifier, otherwise I do not see how that could happen (to sustain oscillation around a stable point), which in the end is what I originally asked.

Best
Tosei

hello chopper,

i forgot to say some my old exp
what do you mean by followers? is it source follower, then i am sure that is causing in presence of the load capacitance. Because i fed-up by this problems once. By connecting follower o/p to the op amp input follower see's big capacitive load.

Thanks,
Raj.  

hi raja,

Thanks for the inputs. I was not aware of the parasitic feedback issue you pointed out. And yes, I was referring to a source follower, but again, the stability analysis around the operating point was indicating the loop was stable even with the source follower in place. I'll check the parasitic feedback and the bias current oscillations.  It should be related to one of these.

Best
Tosei

Hi Tosei,

did I understand well that oscillations could be observed only during ramping the supply voltage?
In this case, I wouldn't rely to much on circuit simulation because many models behave unrealistic for supply voltages that not in the "correct" range (as supposed by the model maker) - in particular when they are not constant.

raja.cedt wrote on Jan 13^th, 2012, 5:30am:


Hi Raj,
what is your question? (My remark was for simulation only!).