Designer’s Guide Community

Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.

Sep 9^th, 2024, 7:13pm

The Designer's Guide Community Forum › Design › Analog Design › Oscillation condition on neg fbk loop: can it be sustained at stable op-points?

‹ Previous topic | Next topic ›

Pages: 1 2

Oscillation condition on neg fbk loop: can it be sustained at stable op-points? (Read 13120 times)

HdrChopper

Community Fellow

Offline

Posts: 493

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #15 - Jan 13^th, 2012, 7:13am

buddypoor wrote on Jan 13^th, 2012, 5:12am:

Hi Tosei,

did I understand well that oscillations could be observed only during ramping the supply voltage?
In this case, I wouldn't rely to much on circuit simulation because many models behave unrealistic for supply voltages that not in the "correct" range (as supposed by the model maker) - in particular when they are not constant.

hi buddypoor,

Yes, you got it right: oscillations could be observed during ramping of supply voltage and were slowing damped till they fade away (as if the circuit was barely stable).
I agree also the models behave unrealistically under those type of transients, but I want to make sure it will not create any oscillation in real silicon.
Anyways, it seems from latest sims that the bias currents are the one to blame in my set up, which aligns with Vladislav suggestions.

Best
Tosei

Keep it simple

IP Logged

HdrChopper

Community Fellow

Offline

Posts: 493

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #16 - Jan 13^th, 2012, 7:14am

raja.cedt wrote on Jan 13^th, 2012, 4:48am:

hello tosie,
yes you are correct, source follower stability problem will be detected by STB analysis. Regarding parasitic feedback please find the schematic where i faced this parasitic feedback

Thanks,
Raj.

Raj,

That is pretty much the same topology I have with the addition of the source follower I mentioned before.

Thanks
Tosei

Keep it simple

IP Logged

raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points? Reply #17 - Jan 13^th, 2012, 11:23am hello tosie, if you are using same architecture then better use different bias for tail node as well as pmos load, if you get rid of oscillations then you are done. I doubt weather .stb will catch this or not. Thanks, Raj.
Back to top	IP Logged

despap

Junior Member

Offline

Posts: 18

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #18 - Jan 14^th, 2012, 12:49am

Problem statement i understood:

- Circuit is excited with supply ramp 0 -> VCC
- Circuit starts to show oscillations at the ouptut
- Oscillations starts to damp once supply stabilizes
- System dosent continue to oscillate for-ever

Couple of doubts here:
- When you did STB analysis, is it at stable supply?
- Are Load conditions are same for:
1. STB analysis
2. Supply ramp sim where osc are observed

IP Logged

raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points? Reply #19 - Jan 14^th, 2012, 2:38am despap, What is the meaning of "When you did STB analysis, is it at stable supply", because STB is for given operating point. Thanks, Raj.
Back to top	IP Logged

Vladislav D Community Member Offline Posts: 76 The Netherlands	Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points? Reply #20 - Jan 14^th, 2012, 3:30am raja.cedt wrote on Jan 14^th, 2012, 2:38am: despap, What is the meaning of "When you did STB analysis, is it at stable supply", because STB is for given operating point. Thanks, Raj. And also for a one feedback loop, whereas in a circuit u have tens of loops
Back to top	IP Logged

despap

Junior Member

Offline

Posts: 18

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #21 - Jan 14^th, 2012, 6:50am

@Raj
Yes..STB is at a operating point.

For this case i assume give operating point is at operating VCC. ( Vcc lets say 5V)

Where as oscillations are observed during supply ramp ( that is VCC < 5V), for which stability cant be commented unless its qualified for those supply values also, which exactly is the case for supply ramp.

Since STB can-not be performed ( rather not practical) for VCC ranging from 0 to 5V ( 5V here is representative), generally supply ramp transient verification is done to qualify the stability.

Correct me anything wrong.

IP Logged

raja.cedt

Senior Fellow

Offline

Posts: 1516
Germany

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #22 - Jan 14^th, 2012, 7:16am

hello despap,
yes you are correct, stb can be done only for a single operating point. But what i mean to say for example if a circuit is stable at 5V means if any disturbance occur to the ckt (may be slight change in the supply from 5V, or could be some common mode disturbance due to couple ) it has to restore it's previous state. So what i feel is if tosie verifies ckt stability at 5V it's okay to carry on.

But one thing i want to tell you is normally supply ramp will be done in transient to check is there any start-up issue (of course it make sense in +ve feedback ckts)

Thanks,
Raj.

IP Logged

despap

Junior Member

Offline

Posts: 18

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #23 - Jan 14^th, 2012, 7:23am

@Raj
It will eventually stabilize with supply ramp. Oscillations will die down.

but with finite parasitics on VCC/GND paths..its always recommended to minimize oscillations during supply ramp.

Start-up is one check during supply ramp sims. But its not all. Ringing behavior should be looked for during supply ramp which actually gives how sturdy is a circuit.

with the presence of other circuits in the system, its potentially dangerous to have oscillations during supply ramp,which might actually end-up sustaining.

IP Logged

raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points? Reply #24 - Jan 14^th, 2012, 8:14am hello, yes, you are talking for supply inductance and all, which will be present any how and they don't die may be because of continues switching or some thing else. Any how good discussion. Thanks, Raj.
Back to top	IP Logged

Dan Clement

Community Member

Offline

Posts: 95
Salt Lake City, Utah, USA

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #25 - Jan 16^th, 2012, 7:26pm

Where does the bias current for the amp and the follower come from?

You may need to delay or ramp the reference voltage until the bias currents are stable.

Are you sure the current densities are rationed properly in the folded cascode ota? You could look for systematic offset as a clue.

The simulator is telling you something. Proceed with caution.

IP Logged

HdrChopper

Community Fellow

Offline

Posts: 493

Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Reply #26 - Jan 19^th, 2012, 5:17am

Dan Clement wrote on Jan 16^th, 2012, 7:26pm:

Where does the bias current for the amp and the follower come from?

You may need to delay or ramp the reference voltage until the bias currents are stable.

Are you sure the current densities are rationed properly in the folded cascode ota? �You could look for systematic offset as a clue.

The simulator is telling you something. Proceed with caution.

Dan,

I checked the bias are properly rationed in the FC ota. I found the bias currents are the ones oscillating during VCC ramp. Actually, these currents are generated by the same voltage reference the ota is buffering: this means the ota buffers a voltage reference which seems to be affected by the loading effect the ota creates on it . This loading effect is two-fold: capacitive loading from ota input and resistive loading since bias currents are generated from voltage reference.

Bottom line: the ota is not the one oscillating, but the voltage reference it is buffering (and loading). This oscillation shows up while VCC is ramping up, and finally vanishes after a very long time, indicating an extremely low dumping factor.

Best
Tosei

Keep it simple

IP Logged

Pages: 1 2

‹ Previous topic | Next topic ›