Jacki
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Hello,
Now I am designing a fully differential switched-capacitor amplifier with gain of 2. At the sampling phase, both the sampling capacitor and hold capacitor are sampled. Then at the hold phase, all of the charges are transferred to hold capacitor. Cs=Ch=350fF. The basic specifications of the operational amplifier are as follows: gainbandwidth 600MHz, DC gain 73dB, phase margin 65 degree.
If I use ideal switches from Spectre analogLib, the PAC simulation is quite good, perfect 2 times amplification. But when I use the real switches (NMOS transistors), the PAC simulation will change as the device size is change.
I want to ask how to hand-calculate the PAC gain of SC-amplifier by using the device models, like Ron (on resistor of the switch), and fs (sampling frequency). Then I can estimate the transfer function of the SC-amplifier. Previously I have some experience on calculation of the gain of mixer and multiplier. I don't know if they are similar because for mixer and multiplier, they also work in the case "on" and "off", like a switch.
Any comments or reported references are highly appreciated.
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