Designer’s Guide Community

boe

Community Fellow

Offline

Posts: 615

Re: voltage leakage in VCO's switching capacitor
Reply #15 - Feb 06^th, 2012, 1:05am

YCY,
YCY wrote on Feb 3^rd, 2012, 4:45pm:

...
I probed the gate current and found it is exactly equal to the drain current but has opposite sign.
Does this mean the current flowing out of the Minus terminal of the Cap (I(/C2/Minus)) all goes to the gate terminal?

Yes, it does.

Quote:

Hi loose-electron

I agree with you. There must be something wrong in simulator setup.
However I cannot find where.

What are your settings for gmin and cmin? Are they negligible compared to the impedances of your circuit elemens?
- B O E

Back to top

IP Logged

YCY

Community Member

Offline

Posts: 32

Re: voltage leakage in VCO's switching capacitor
Reply #16 - Feb 6^th, 2012, 6:12pm

boe wrote on Feb 6^th, 2012, 1:05am:

YCY,
YCY wrote on Feb 3^rd, 2012, 4:45pm:

...
I probed the gate current and found it is exactly equal to the drain current but has opposite sign.
Does this mean the current flowing out of the Minus terminal of the Cap (I(/C2/Minus)) all goes to the gate terminal?

Yes, it does.

Quote:

Hi loose-electron

I agree with you. There must be something wrong in simulator setup.
However I cannot find where.

What are your settings for gmin and cmin? Are they negligible compared to the impedances of your circuit elemens?
- B O E

Hi, B O E

I set gmin from 1e-12 to 1e-15, and it does affects the results.
The smaller the gmin, the longer the discharging time.
As for cmin, it seems to have no influence on the simulation results.
I tried to set cmin to 0, 0.1f, and 1f.

BTW, now I think nrk1 is right.
The reverse-biased diode between drain/bulk is the main cause that discharges VD to 0V.
Because if I connect bulk to 1.2V, VD will be charged to 1.2V rather than 0V.

But I still do not know why the current flowing out of the cap is not equal to that flowing into the NMOS.

Thanks,
YCY

Back to top

IP Logged

nrk1

Community Member

Offline

Posts: 81

Re: voltage leakage in VCO's switching capacitor
Reply #17 - Feb 6^th, 2012, 6:28pm

Hi,

Strange. Not sure if D/S/B terminal currents which are probed include currents in the drain/source diodes. Some experiments to check:
1. Increase AD/PD of the MOS and see if the rate or droop increases.
2. Connect an identical MOS transistor with drain and source to the present circuit's drain, and gate to the present circuit's gate. Check if the rate of droop increases(because of extra diodes).

YCY wrote on Feb 5^th, 2012, 9:35pm:

nrk1 wrote on Feb 4^th, 2012, 6:02am:

YCY,

Is the nMOS bulk connected to source or 0V? ...

Hi, nrk1

Yes the bulk is connected to 0V.
But the bulk current is near 0A, thus I guess it not the main cause.

Back to top

IP Logged

YCY

Community Member

Offline

Posts: 32

Re: voltage leakage in VCO's switching capacitor
Reply #18 - Feb 6^th, 2012, 7:31pm

nrk1 wrote on Feb 6^th, 2012, 6:28pm:

Hi,

Strange. Not sure if D/S/B terminal currents which are probed include currents in the drain/source diodes. Some experiments to check:
1. Increase AD/PD of the MOS and see if the rate or droop increases.
2. Connect an identical MOS transistor with drain and source to the present circuit's drain, and gate to the present circuit's gate. Check if the rate of droop increases(because of extra diodes).

YCY wrote on Feb 5^th, 2012, 9:35pm:

nrk1 wrote on Feb 4^th, 2012, 6:02am:

YCY,

Is the nMOS bulk connected to source or 0V? ...

Hi, nrk1

Yes the bulk is connected to 0V.
But the bulk current is near 0A, thus I guess it not the main cause.

Hi nrk1,

I think your previous post (#11) is right, the reverse-biased diode between D/B results in the leakage of VD.
Because if I connect bulk to 1.2V, VD will be charged to 1.2V rather than 0V.
Thanks for your suggestion.

YCY

Back to top

IP Logged

boe

Community Fellow

Offline

Posts: 615

Re: voltage leakage in VCO's switching capacitor
Reply #19 - Feb 7^th, 2012, 10:15am

YCY wrote on Feb 6^th, 2012, 7:31pm:

...
Hi nrk1,

I think your previous post (#11) is right, the reverse-biased diode between D/B results in the leakage of VD.
Because if I connect bulk to 1.2V, VD will be charged to 1.2V rather than 0V.
Thanks for your suggestion.

YCY

If you connect the bulk of the nMOS to 1.2V, you will forward-bias the drain-bulk diode if V_D < 1.2V.
- B O E

Back to top

IP Logged