Hi,

I am designing an RF VCO with switching capacitors, whose oscillation frequency is around 3GHz.
The switching cap cell in the off-state is simplified as:



The voltage V_D is precharged to a value near 0.8 V to assure the NMOS is off when its gate is switched to ground.
However, when I do the transient analysis and set a very long stop time, say 10us,
the voltage V_D starts to drop to near 0V.
I don't think the voltage drop comes from the leakage current of the NMOS, if so,
the voltage should be pulled up to 1.2V but not drop to 0V.

I also find that the speed of voltage drop is related to the accuracy of transient analysis.
The simulation results is shown below
(liberal, moderate, conservative are the errpreset, pointlocal is conservative with relref=pointlocal, reltol=1e-5 is conservative with reltol=1e-5
The dropping speed is liberal>moderate>conservative>pointlocal>reltol=1e-5)

I cannot figure out how the accuracy setting affects this simulation result.
Does anybody have any idea about this phenomenon?
Thanks in advance.

YCY

boe wrote on Feb 2^nd, 2012, 5:01am:


Agreed with Boe.

Also, you need to recognize that a capacitor has leakage (outside the simulator accuracy, this is a different issue) so do not expect to precharge a capacitor, and have it maintain that voltage for long periods of time.

loose-electron wrote on Feb 2^nd, 2012, 2:21pm:


Hi, loose-electron

Thanks very much for your reply.
I also doubted the cap leakage in the begging,
so I replaced it with an ideal one.
Yet the leakage remains the same.

Besides, all the dc voltages in the circuit are much higher than 0V.
Thus I used to think that even leakage exists, V_D will be charged to a higher voltage but not pulled down to 0V.
But the simulation result shows the opposite.

regards,
YCY

YCY,
YCY wrote on Feb 2^nd, 2012, 5:47pm:
Note that typically reltol*i >> iabstol. Error limit is abs(i)*reltol + iabstol, where i is influenced by relref.

Quote:
Check the gate and bulk currents for capacitive coupling from node V_D to gate/bulk. You will find that they are not part of the drain current.

- B O E

boe wrote on Feb 3^rd, 2012, 6:19am:


Hi, B O E

Since I probe the drain terminal to get the current waveform,
I do not know how to check the current that flows from V_D to gate/bulk.
Could you please state more specifically on this?
Thanks a lot.

YCY

boe wrote on Feb 3^rd, 2012, 8:26am:


Hi B O E

The MOS device I used is a 4-terminal transistor.
I probed the gate current and found it is exactly equal to the drain current but has opposite sign.
Does this mean the current flowing out of the Minus terminal of the Cap (I(/C2/Minus)) all goes to the gate terminal?
Besides, the source and bulk currents are all negligibly small.
So, it still confuses me why I(/C2/Minus~19uA) is not equal to I(M1/D~6uA), where goes the remaining 13uA (I(M1/S) & I(M1/B)<<1pA, )?

Thanks
YCY

YCY wrote on Feb 2^nd, 2012, 6:35pm:



You need to take a close look at the
tolerance and error settings in your simulator setup.

My earlier comment about real world capacitors
having plate to plate leakage is still valid, but the
problem you showing here is probably simulator
error tolerance settings and their setup.

loose-electron wrote on Feb 4^th, 2012, 7:42am:


Hi loose-electron

I agree with you. There must be something wrong in simulator setup.
However I cannot find where.

I tried several different settings, such as tightening  reltol from 1e-3~1e-7 and iabstol from 1e-12~1e-15,
yet the currents from cap and into NMOS are still not equal.
I have also tried tightening gmin, which affects the discharging time of V_D.
Smaller gmin leads to longer time.
Nevertheless, the cap current and NMOS drain current are still not the same.

Do you have any suggestion about the accuracy settings that I can try to verify the circuit?

Thanks a lot
YCY