The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 17th, 2024, 4:39pm
Pages: 1
Send Topic Print
VHDL and Verilog AMS Co-Simulation (Read 1805 times)
despap
Junior Member
**
Offline



Posts: 18

VHDL and Verilog AMS Co-Simulation
Feb 17th, 2012, 9:39am
 
Hi all,,
Is it possible to simulate VHDL,Verilog-A and Spectre together for AMS flow.
I have a VHDL code for a block and Verilog-A behavioral model for an analog block and one more transistor level block.
I checking any flows to simulate these three together.

Any ideas/help folks..!!

Thanks.!
Back to top
 
 
View Profile   IP Logged
boe
Community Fellow
*****
Offline



Posts: 615

Re: VHDL and Verilog AMS Co-Simulation
Reply #1 - Feb 23rd, 2012, 3:38am
 
despap,

Yes, that is possible.

- B O E
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.