Lex wrote on Mar 2nd, 2012, 4:57am:The way I see it, there are two things that makes the use impracticable.
i. The redundant capacitance reduces the power efficiency of ADC in such a way that you actually don't need such small capacitors in the first place. This part you refer to as 'negligible' effect.
You may be correct, but I didn't look closely enough at it to determine if what you say is true. Their power numbers are very low.
Quote:ii. They don't have the adequate tools to model the capacitance. I don't think it is a matter of variance, as they call it themselves "systemic layout issues" that go undetected.
As we say, cowboy up! ;D You might recall that I don't have a lot of faith in models anyway, and I don't think designers should. I personally am ok with this sort of stuff if it is really needed as long as the limitations are known, but I "grew up" with much less sophisticated modeling. You have to take some rough estimates of the parasitics and also use designs that are insensitive to it. On the other hand, you wouldn't want to use these tiny capacitors if you can get the performance with a better modeled topology!
Quote:I didn't see any calibration either. What kind of calibration do you suggest for such a small capacitor array? Correct it digitally afterwards?
My point was that calibration isn't needed in spite of the very small capacitance so they must be doing something correct.
I'm seeing so many papers with super low power numbers but they are using "calibration" to fix a design that is super sensitive to PVT. I'm not comfortable intentionally doing those types of designs even if I just wanted a paper, but (without looking to closely at it) this design seems like something I'd try if I really needed whatever the heck they needed. :)