RobG wrote on Feb 28^th, 2012, 7:55am:


Thanks for the paper Rob!

To me, what is striking is that they conclude that the systemic DNL is dominating, suggesting systematic layout issues for which they say that they are not detected by the extraction tool. No extra words are spent on this very important matter. So basically they have a fancy, self built, (EM?) extractor which does not correspond to the actual thing. That is not really assuring if you have to explain this to a customer.

Next, the fact that they have a total capacitance of 377fF of which 251fF is redundant, just shows this is another academic shot to score a paper at a conference. Which is of course legitimate, since funds depends on of accepted papers. But in essence it shows that you do not gain much by using such small capacitors.

Anyhow again thanks for the paper, but to me it advocates not to use such small capacitors.

Lex wrote on Mar 1^st, 2012, 2:21am:


I haven't looked at it closely so I can't tell if it is practical or if I'm missing something. Not sure what you mean by redundant, or if it matters. The parasitics on the bottom side should have negligible effect since that side is switched. And parasitics on the top side only attenuate the signal provided to the comparator. This will cut into your SNR, but won't affect DAC linearity.

What do you think? I didn't see where any calibration was done but could have missed it.

rg

Lex wrote on Mar 2^nd, 2012, 4:57am:

You may be correct, but I didn't look closely enough at it to determine if what you say is true. Their power numbers are very low.
Quote:

As we say, cowboy up!  ;D You might recall that I don't have a lot of faith in models anyway, and I don't think designers should. I personally am ok with this sort of stuff if it is really needed as long as the limitations are known, but I "grew up" with much less sophisticated modeling. You have to take some rough estimates of the parasitics and also use designs that are insensitive to it. On the other hand, you wouldn't want to use these tiny capacitors if you can get the performance with a better modeled topology!

Quote:

My point was that calibration isn't needed in spite of the very small capacitance so they must be doing something correct.

I'm seeing so many papers with super low power numbers but they are using "calibration" to fix a design that is super sensitive to PVT. I'm not comfortable intentionally doing those types of designs even if I just wanted a paper, but (without looking to closely at it) this design seems like something I'd try if I really needed whatever the heck they needed.  :)

nus_lin wrote on Feb 23^rd, 2012, 8:47pm:


You can remove device instances for the unit caps from the netlist, and treat all capacitive components as parasitic - AND use a high-precision capacitance extraction tool based on a field solver.
this will give you a much more reliable capacitance results - both intended capacitance and parasitic coupling capacitance values - as SPICE models for the capacitors are not accurate at all for small capacitors that are exposed to the outside world (i.e. not properly shielded) and that have large parasitics.

Here is a couple of relevant links:

http://www.electronics-eetimes.com/en/faraday-selects-silicon-frontline-s-f3d-fo...

http://www.edaboard.com/thread159589.html