Hi

I tried to import a Not Gate verilog in to Virtuoso (IC 6.1.3.1) through the verilog in form
the not gate code :

module notgate(b,a);
output b;
input a;
assign b =~a;
endmoudule

after i imported it i created a schematic cell view with the input of not gate as a pulse voltage source (voltage varying from 0 to 1.8V with rise time 1ns, fall time 1ns, pulse width as 5ns and time perion as 10ns)
and the output was attached to an output pin
later i created its config view with AMS template
in the ADE L window i selected AMS simulator, gpdk.scs as model library ans spectre as solver
when i do run the ADE i get an output waveform that has no values in its y axis
my specctre version is 78.2.0
what could be the possible source of error
if i had missed any piece of information kindly point it out
regards
deepak

Hi

I am sorry if posted anything wrong
I am new to Cadence tools
The version of spectre i posted is what i got by typing "which spectre"
i guess i had copied it correctly
at the moment i away from college which has these Cadence tools
will post about the versions of INCISIV once I go there

Yes I am running a Transient simulation.
And in the output i could see the waveform and it behaves as expected (i.e. high when input is low and low when input is high) but only that the y-values are not there

I am using 5V connect modules (though i tried with 1.8V and 3V modules as well but there was no difference)

i am including only "gpdk.scs" as Model Library
i tried to include nmos1.scs and pmos1.scs it shows error
is there anything else i should add

regards
deepak

Hi,
one more thing:
deepak srinivasan wrote on Feb 27^th, 2012, 7:12am:
You seem to work on a 1.8V design (according to your initial post), so you should use 1.8V CMs as well.

- B O E

You seem to work on a 1.8V design (according to your initial post), so you should use 1.8V CMs as well.///

yes i tried with 1.8 V CM
and i changed the input to 5V and tried with 5V CM as well
but there is no difference in the output

Deepak srinivasan,
the digital model you gave in the initial post of this thread has neither power consumption nor delay. If you want to measure delay and power you need a transistor-level model (implementation).

- B O E

deepak srinivasan wrote on Feb 28^th, 2012, 3:38am:
Yes, there are ways to estimate and model delay and power consumption of digital (gate-level) blocks/cells based on characterization of individual gates on transistor level, e.g. timing analysis (for delay).
- B O E

Hi

Can anyone please help me by providing link to a tutorial on finding delays for digital blocks
i am unable to find it

regards
deepak