Hello all,
I am using assura 3.1.6 USR 1 with IC 5141 hotfix and also with UMC 90nm technology. DRC (by setting some switches) and LVS ran successfully for my simple inverter layout but RCX gave the following error.
capgen Capgen results will be written to directory: /home/vinay_rao/work/test2
*ERROR* at "capgen": -blocking mask layer 'NCAPGATE_25' not defined in LVS file quitting.
Forking:/cad/cadence/ASSURA316/tools/assura/bin/32bit/capgen-techdir /home/vinay_rao/work/foundry/umc90/RuleDecks/Assura/LVS/../LPE/Option13 -lvs /home/vinay_rao/work/test2.xcn -p2lvs /home/vinay_rao/work/foundry/umc90/RuleDecks/Assura/LVS/../LPE/Option13/p2lvsfil
e -sw3d -add_via_effect me1,dif -blocking RFSYMBOL,sub,dif,ply,me1,me2,me3,me4,me5,me6,me7,me8,me9,alrdl -res_blocking RFSYMBOL,PLY,M1,M2,M3,M4,M5,M6,M7,M8,M9,AL_RDL -blocking NCAPGATE_10,ply,dif,sub -blocking NCAPGATE_12,ply,dif,sub -blocking NCAPGATE_25,ply,dif,sub -blocking NCAPGATE_HVT_10,ply,dif,sub -blocking NCAPGATE_HVT_12,ply,dif,sub -blocking NCAPGATE_N_25,ply,dif,sub -length_units meters -p ply,Allgates,dif -cap_unit 1 /home/vinay_rao/work/test2
*WARNING* Bad return status from RCX script generator. 0x100

I also went through the post
http://www.cadence.com/Community/forums/p/13908/22563.aspx which has noted about the same error but I didn’t find ‘resimulate_extracted’ switch set (as it is foundry dependent). And I didn’t understand clearly about Quek reply.

Can anyone suggest me how to resolve this for UMC files?
Regards,
Vinay Rao.