aaron_do
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Hi,
thanks. Yes I suspected the answer was as simple as that. So can anybody tell me what kind of loop bandwidth is possible and roughly how much power consumption it would take?
So I want to actually divide from 2 GHz to some reference frequency (up to me to define), but I need my loop bandwidth to be large. Is it possible to achieve a 100 MHz loop bandwidth? I understand that for an integer-n PLL, the reference frequency is usually around 10* the loop bandwidth. So does that rule out such a simple architecture?
thanks, Aaron
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