hello
i have a problem, i simulate a latch comparator with stb analysis
the schematic is below
![](http://desmond.imageshack.us/Himg39/scaled.php?server=39&filename=im3t.jpg&res=medium)
i got a negative phase loop which means the feedback is negative, i can't figure out from where comes this negative feedback or is ir an artifact !!!
![](http://nsa22.casimages.com/img/2012/03/27//120327011851748833.jpg)
now i removed the cross coupled pmos pair in the top
like this
![](http://nsa22.casimages.com/img/2012/03/27//120327012011954358.jpg)
and now the feedback is positive,
![](http://nsa21.casimages.com/img/2012/03/27//120327012117924339.jpg)
i am really confused , please help me figuring out what's going on
regards