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negative feedback in latch comparator (Read 838 times)

ellarguero

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Posts: 9

negative feedback in latch comparator
Mar 27^th, 2012, 4:10am

hello

i have a problem, i simulate a latch comparator with stb analysis
the schematic is below

i got a negative phase loop which means the feedback is negative, i can't figure out from where comes this negative feedback or is ir an artifact !!!

now i removed the cross coupled pmos pair in the top

like this

and now the feedback is positive,

i am really confused , please help me figuring out what's going on

regards

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raja.cedt

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Germany

Re: negative feedback in latch comparator
Reply #1 - Mar 27^th, 2012, 5:05am

hello,
what is the intention of doing behind doing .STB for a latch or what is interested parameter from this simulator?

Any how your Question is valid. What is the exact phase at at 1meg. Due to +ve feedback you +ve phase shift, but due to gds of the pmos and nmos you get _ve phase shift as well. So don expect pure +ve FB.for example if gds is grater than gm then there is -ve feedback rather +ve feedback.

Thanks,
Raj.

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ellarguero New Member Offline Posts: 9	Re: negative feedback in latch comparator Reply #2 - Mar 27^th, 2012, 6:32am hi Raj the intention is just to understand i believe the fb is always positive wether gds>gm or not, now if gm<gds the loop gain is not enough to induce latch i think there is an extra negative feedback du to the common source node (the drain of the current tail). i am trying to figure out how does it work
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: negative feedback in latch comparator Reply #3 - Mar 27^th, 2012, 1:35pm hello, source node will be at ac ground, so how it will present -ve fb?
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