Hi Guy,
It is weird that Dout is always kept HiZ during the simulation.
The code is almost the same as that E2L_2_inhconn in built-in connectLib. I paste the code in the following.
Code:// INCLUDE FILES:
`include "disciplines.vams"
`timescale 1ns / 100ps
//============================================================================
connectmodule E2L_2_inhconn (Ain, Dout);
input Ain; electrical Ain; // electrical input
output Dout; \logic Dout; // logic output
// Inherited vdd! and vss!
electrical
(* integer inh_conn_prop_name="PVDD";
integer inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd! ;
electrical
(* integer inh_conn_prop_name="NVSS";
integer inh_conn_def_value="cds_globals.\\vss! "; *) \vss! ;
// INSTANCE PARAMETERS:
parameter real tr=0.2n from (0:1m); // risetime (for defaults)
parameter real txdel=4*tr from (0:1m); // time midrange til output X
parameter real ttol_c=tr/4 from (0:1m); // time tolerance of crossing
// scaled input/output levels/thresholds (0 maps to Vref, 1 maps to Vsup):
parameter real vthi=1/1.5 from (0:1); // frac. for high tresh (def=2/3)
parameter real vtlo=vthi/2 from (0:vthi); // frac. for low tresh (def=1/3)
parameter real vtol=1.0/12 from (0:(vthi-vtlo)/2]; // frac. for vtol
parameter real vtlox=vtlo+vtol from (vtlo:vthi); // lo to X state threshold
parameter real vthix=vthi-vtol from [vtlox:vthi); // hi to X state threshold
// LOCAL VARIABLES:
reg Dreg; // output register
reg Xin; // Tx control registers
real Kin; // input relative to supply range
real txdig; // tx in timescale units
//============================================================================
initial begin
txdig=txdel/1n; // digital delay midlevel to X (ASSUMES TIMESCALE)
Dreg=1'b0; // initial level
Xin=0; // initially not in X delay region.
end
// Relative input level (maps input to range of 0=vref, 1=vsup):
analog Kin = V(Ain,\vss! )/max(V(\vdd! ,\vss! ),1m);
// Convert analog signal to high/low and X/notX:
always @(above(Kin-vthi,ttol_c,vtol))
begin Dreg=1; Xin=0; end // analog XtoH
always @(above(vtlo-Kin,ttol_c,vtol))
begin Dreg=0; Xin=0; end // analog XtoL
always @(above(vthix-Kin,ttol_c,vtol))
if (Dreg==1'b1) Xin=1; // analog HtoX
always @(above(Kin-vtlox,ttol_c,vtol))
if (Dreg==1'b0) Xin=1; // analog LtoX
// Wait for txdel before driving output to X:
always @(posedge(Xin)) begin // input changed to X
#(txdig) // wait for X time delay
if (Xin==1) Dreg=1'bx; // goto X if still between
end
assign Dout=Dreg; // assign register to output
always @(Dout) begin
$display($time, "\t Dout = %1b \n", Dout);
end
always @(Dreg) begin
$display($time, "\t Dreg = %1b \n", Dreg);
end
endmodule
The always block @(Dout) and @(Dreg) are for monitoring the toggle of Dout and Dreg. It is curious that Dout is always HiZ although Dreg toggles.
My tools are IC6.1.4.500.10, and MMSIM 11.1.0.249.isr2, and INCISIVE 10.20-s043.
Any comments are appreciated.
Yawei