Hi guys (and ladies
),
I'm trying to find a way to calculate the power consumption over nMos during a switch (V
G turns from 0 to 1 logic).
Lets assume my circuit is made of a DC power supply V
DD, connected serially to a resistor R and an nmos transistor.
Calculating the area under the graph I
D(V
D) (using P=IV) isn't gonna work, because there's no time aspect there..
I thought I could model the transistor as a resistor R
nmos with a capacitor in parallel C
nmos,
this way I can treat R
nmos as the one who's current is I
D.
This way after (transistor's) Tau~RC the transistor reaches saturation (the capacitor C
nmos is "disconnected" after T=inf so all the current goes through R
nmos).
Is that a correct observation?
If it is, I'm not sure how can I determine C
nmos.
About the R
nmos - I can use a "zero-order" approximation by determining R
nmos = V
DD/I
saturation , since after the capacitor charges, the R, R
nmos are serial connected.
Thanks,
Gil.