Hi guys (and ladies ),

I'm trying to find a way to calculate the power consumption over nMos during a switch (V_G turns from 0 to 1 logic).

Lets assume my circuit is made of a DC power supply V_DD, connected serially to a resistor R and an nmos transistor.

Calculating the area under the graph I_D(V_D) (using P=IV) isn't gonna work, because there's no time aspect there..

I thought I could model the transistor as a resistor R_nmos with a capacitor in parallel C_nmos,
this way I can treat R_nmos as the one who's current is I_D.
This way after (transistor's) Tau~RC the transistor reaches saturation (the capacitor C_nmos is "disconnected" after T=inf so all the current goes through R_nmos).

Is that a correct observation?

If it is, I'm not sure how can I determine C_nmos.
About the R_nmos - I can use a "zero-order" approximation by determining R_nmos = V_DD/I_saturation ,  since after the capacitor charges, the R, R_nmos are serial connected.

Thanks,
Gil.  

AnalogDE wrote on Apr 25^th, 2012, 2:03pm:


This seems like a homework problem so I don't want to give the answer, but I think you have the right approach. If you don't have the information to calculate Cnmos you can't include the transient part. Likewise, if you don't have a time period it doesn't make sense to do the transient portion since you don't know how much it contributes to the overall power.

rg