Hello all,

I am currently trying to design the analogue part of a 2nd-order sigma-delta ADC. My bandwidth is 1KHz and I need to achieve SNDR > 98dB (16bits).

I have started with some Matlab-Simulink simulations base on the SigmaDelta Toolbox. The only non-desired effect I am considering so far is just the switch non-linearity and the KT/C noise. Both integrators are ideal and there is no saturation in the system.

I have implemented the same system in my spice simulator. Ideal integrators and comparator.

When simulating both systems under same conditions, I have found that the schematic simulation has odd harmonics, which are not visible with Simulink. These harmonics ruin my SNDR so results are different from expected.

I have seen other people having the same issue as me but, I still don't know where these harmonics come from or how to reduce them.

Even with ideal components, are odd-order harmonics a common issue in SD-ADCs?

Thank you in advance to everyone providing some feedback.