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Questions about modeling jitter in PLL (Read 2520 times)
Chris Yang
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Questions about modeling jitter in PLL
Jun 17th, 2012, 7:09pm
 
I followed the paper, Modeling Jitter in PLL-based Frequency Synthesizers, wrote by Ken. I have a question after simulation. I try to verify how the system bandwidth affects the PLL output jitter when the VCO is the only noise source. So, I only put the accumulating jitter in VCO and all other blocks are ideal. I find that the output jitter almost doesn't change when I vary the system bandwidth of the PLL. This result doesn't make sense. The output jitter should decrease when I increase the system bandwidth of the PLL because the VCO noise see a high-pass filter. Do I do anything wrong? Does anyone get the same result?

Chris
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yaoxy
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Re: Questions about modeling jitter in PLL
Reply #1 - Dec 4th, 2013, 5:34pm
 
I guess the output jitter you mean is period jitter. I did exact same thing as you did. Only VCO exibits noise. The period jitter changed from 5ps to 4.72 ps as I change C1 from 3.125 nf ro 31.2 nf. And the phase jitter (integrated phase noise) changed from 5.6 us to 5.4 us.

I was hoping that both phase jitter and period jitter have big change since the phase noise wave form change a lot.
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