Hi everyone,

I'm currently designing a two stage folded-cascode op-amp (having 1 uA bias current) with IBM 0.13 um technology. This design passes the corners test, but when I run a monte carlo analysis (mismatch only, 200 iterations) for mismatch in open-loop configuration, I get really bad results.

To find the critical transistors to be matched, I have applied, one at a time, a difference of 20 nm in width between each transistors pairs (Delta Width=20nm)  to be matched.
For the current mirror pairs in the cascode stage (top pmos current mirror transistors and bottom nmos current mirror ), this small delta W difference is very critical, resulting in a huge decrease in open loop gain (from 100 dB at DC, to 40dB and even 0dB). So I tried to increase the area of these transistors (WL), but I still get the same results.

As this is my first op-amp design, is it normal that such a small mismatch affect the results so badly for an op-amp ? If not, how to resolve the problem, else than increasing the transistor area ? Does adding dummies, interdigitation and common-centroid layout techniques would be enough ?

Thanks!

Maybe you have biased your transistors in weak saturation. This gives high gain, but simultaneously high mismatch. You could try sacrificing the gain a bit by decreasing the W/L ratio.