The Designer's Guide Community
Forum
ForumVerilog-AMSAnalysisModelingDesignTheory
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 19th, 2024, 2:44pm
 
  HomeHelpSearchLoginRegisterPM to admin    
The Designer's Guide Community Forum › Other CAD Tools › Physical Verification, Extraction and Analysis › how can i use  asitic  to simulate and design the PGS inductor on chip
‹ Previous topic | Next topic ›
Pages: 1
Send Topic Print
how can i use  asitic  to simulate and design the PGS inductor on chip (Read 1929 times)
coolliu
New Member
*
Offline



Posts: 1
how can i use  asitic  to simulate and design the PGS inductor on chip
Jul 17th, 2012, 7:09pm  
hi everybody!
 I'm a new guy for designing the ic.Now i want to design a PGS(Patterned Ground Shields) inductor  on si chip. can i use the ASITIC to design PGS and get the parasitic parament .where can i get the TMSC18.Tek FILE.
thank you for your concern.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
‹ Previous topic | Next topic ›
« Home ‹ Board
The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.