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The Designer's Guide Community Forum › Design › Mixed-Signal Design › how to handle higher bias current??

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how to handle higher bias current?? (Read 2757 times)

raja.cedt Senior Fellow Offline Posts: 1516 Germany	how to handle higher bias current?? Sep 01^st, 2012, 11:51am hello all, due to some reason i have to use a NMOS with more than the current what it designed for (max contacts ratings), now i would like to ask if i flatten the PCELL and add some contacts will i get any problem? I hope i can extract all the added contact resistance.... Thanks, Raj.
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fredd New Member Offline Posts: 1 Pilipinas	Re: how to handle higher bias current?? Reply #1 - Sep 3^rd, 2012, 2:43am May I know what process you are using?
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: how to handle higher bias current?? Reply #2 - Sep 3^rd, 2012, 4:49am 45nm...
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Lex Senior Member Offline Posts: 201 Eindhoven, Holland	Re: how to handle higher bias current?? Reply #3 - Sep 3^rd, 2012, 7:00am Except for model validity, I don't see really any reason why not. Of course as long as you obey to the DRC/DFM. Could you give some extra details, e.g. how many extra contacts would you need, how many do you have, what is the current (density), etc..
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