lhlbluesky_lhl
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in simulation, i found that, the VO ripple is also related to the load current. during the transition of each period, there is a current peak (200uA or so) for a normal load current of 20uA. if i decrease the current peak in simulation, the ripple also decreases. and the current peak may be caused by digital cells, such as inverter. and is this be ok?
besides, i uploaded the full diagram(1.jpg). RL is actually an osc, and LDO is used to suppress or decrease the power noise. but in simulation, i found that, when i add the power noise at vdd, the noise in VO is also very large, and so, the jitter of osc is ten times larger than non-power-noise case, why? is it related to the psrr+ of LDO? the psrr+ of LDO in low frequency is larger than 75dB. osc frequency is 4M here. why power noise not decreased as expected by using local LDO? is there any problem here?
thanks all for reply.
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