lhlbluesky_lhl
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in osc.jpg, it is the diagram of my osc, the voltage in CL(assuming node VI) is a ramp wave, but in simulation, i found that, the voltage of Vref1 and Vref2 is also changed with VI(ripple is about +/- 10mV), the amplitude is about 2% of VIpk-pk, i guess it is due to the capacitive coupling. and if i increase C1 and C2, or decrease the input pair size of comparator, the ripple in Vref1 and Vref2 decreases too. if i want to make Vref1 and Vref2 stable(ripple as small as possible), and not using very large C1 and C2(for area saving), not using very small input pair size for comparator(for good matching), is there any solution or method?thanks all for reply.
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