raja.cedt
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hello, 1. yes, when you have W1/L1 and W2/L2 size transistors the resulting transistor size from DC characteristics point of view L/W=L1/W1+L2/W2.
2. Effective Vt will be same as top transistor. 3. Coming to device intrinsic mismatch up to it is not effective, the normal saying of larger effective length will not work here. Look reduction of mismatch with bigger size comes from the random averaging theory, instead here effectively you are increasing the size. Let us model bottom triode transistor as a resister (for now assume there is no modulation of resistance due to drain voltage variation). In the contest of degeneration mismatch of the top transistor will be reduced but resister mismatch will introduced, however resister matches better but here this resister emulated by again Mosfet.
4. Noise is worse, because same reason mos noise worse than degeneration.
So bottom line is this combination will be good from low voltage operation point of view and may be worse from other aspects.
Thanks, raj.
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