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rfidea Senior Member Offline Posts: 159 Europe	Re: properties of stacked mos device Reply #15 - Nov 29^th, 2012, 12:35pm One solution is to use four transistors in parallel of W/L=1u/8u as reference transistor with 1uA and then one 1u/8u transistor for the 1/4 uA transistor. Larger layout but probably better matching.
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analog_wiz Junior Member Offline Posts: 31 Universe	Re: properties of stacked mos device Reply #16 - Nov 29^th, 2012, 11:35pm But will it not be bad in the sense that the vth of a 1u/8u and 1u/2u device will not be the same and will lead to a systematic current mismatch error?
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rfidea Senior Member Offline Posts: 159 Europe	Re: properties of stacked mos device Reply #17 - Nov 30^th, 2012, 1:38pm Not if you implement the 4x 1u/8u transistor as four unique transistors. Then the current density of each of them will be the same as the single 1u/8u, which give the same vth and good matching.
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: properties of stacked mos device Reply #18 - Dec 2^nd, 2012, 5:14pm hello rfidea, i guess Vth mismatch will be serious problem in this case. How current density related to Vth (from your previous post). Thanks, Raj.
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rfidea Senior Member Offline Posts: 159 Europe	Re: properties of stacked mos device Reply #19 - Dec 3^rd, 2012, 11:29am Of course, for the specific current the W/L ratio needs to be chosen so the Vgs-Vth voltage is high enough to get the wanted Vth mismatch.
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threepwood

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Re: properties of stacked mos device
Reply #20 - Mar 23^rd, 2013, 6:39am

Interresting topic
Can someone provide mathematical calculation to prove it?

I would extend the question for robust cascode polarization technique below:

I know it works fine, but I've never managed to calculate why. I also think that the 2 (or 3, or 4,...) devices at the bottom (that are in triode region) must match the NMOS bias device...

Can someone try to do the calculations? �:)

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English is not my mother tongue, so please excuse my mistakes ^^

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Horror Vacui Senior Member Offline Posts: 127 Dresden, Germany	Re: properties of stacked mos device Reply #21 - Mar 23^rd, 2013, 12:51pm I doubt whether any calculations should give you a good enough precision. Nowadays the square law MOS characterisitc is far from precise and also you will have one transistor in saturation and all the other in triode region not far from the saturation region.
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Horror Vacui Senior Member Offline Posts: 127 Dresden, Germany	Re: properties of stacked mos device Reply #22 - Mar 23^rd, 2013, 12:52pm Here is an older topic: http://www.designers-guide.org/Forum/YaBB.pl?num=1162979112
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threepwood

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Re: properties of stacked mos device
Reply #23 - Mar 23^rd, 2013, 1:08pm

Horror Vacui wrote on Mar 23^rd, 2013, 12:51pm:

I doubt whether any calculations should give you a good enough precision. Nowadays the square law MOS characterisitc is far from precise and also you will have one transistor in saturation and all the other in triode region not far from the saturation region.

They are all deeply linear (with VDS=5,10,15mV,..) and the device at the top, even if the square law is not accurate, I just would like to get a trend

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English is not my mother tongue, so please excuse my mistakes ^^

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