hello,
1. yes, when you have W1/L1 and W2/L2 size transistors the resulting
transistor size from DC characteristics point of view L/W=L1/W1+L2/W2.

2. Effective Vt will be same as top transistor.
3.       Coming to  device intrinsic  mismatch up to it is not effective, the normal saying of larger effective length will not work here. Look reduction of mismatch with bigger size comes from the random averaging theory, instead here effectively you are increasing the size.
       Let us model bottom triode transistor as a resister (for now assume there is no modulation of resistance due to drain voltage variation). In the contest of  degeneration mismatch of the top transistor will be reduced but  resister mismatch will introduced, however resister matches better but here this resister emulated by again Mosfet.

4. Noise is worse, because same reason mos noise worse than degeneration.

So bottom line is this combination will be good from low voltage operation point of view and may be worse from other aspects.

Thanks,
raj.
     

I agree with raja that in principle you can add the two lengths. But I wonder why you would like to stack two devices. I would have increased the length and only use one transistor. Usually there is some limitation in the design kit, but that is the length need to be shorter than some 25 um or so.

Aha, I did not know that Lmax was that low for those processes. I do not understand why, though. Is there any technical reason other than logistical such as testing and modeling efficency.

I dont think there is any limit on the length say 5u in smaller gomentries. The only time i use devices in series is to get some very small current mirrored eg:1/2:1/8 (1/8=four 1/2 devices in series).

@ analog_wiz,
Can you please explain clear why did you use stacked devices?,i were you i would have done  2:1 mirroring directly rather than using stacked devices, up to me stacked device is equivalent to larger length device, but up to me mismatch will be bad for this combination.

Did you find any reduction in the noise or mismatch, because  yvkrishna noticed reduction in mismatch i just want to check is it consistent with every one.

@Lex  : i heard mainly fabrication limitation due to introduction of Double-pattern lithography metal gate technologies in lower technologies and orientation limitation due to modeling(i am not sure) . What is ELT?  

Thanks,
Raj.

hello Lex,
interesting, this i knew this with name donnet transistor, but haven't seen in any technology.Which foundry is providing this?

Thanks,
Raj.

pls see this in fig5 and the text above it.

http://www.design-reuse.com/articles/28591/mixed-signal-ip-design-challenges-in-...