RFICDUDE wrote on Oct 16th, 2012, 4:37am:...but I do know that PSS convergence is sensitive to the value of "tstab" when simulating switched circuits such as dividers, PFD and inverters.
The PSS start and finish points for the fundamental need to be on the rising or falling edge of a signal that is periodic with fundamental.
Thanks RFICDUDE,
Does that means that if I want to simulate PSS for a PLL, I should set "tstab" much larger than the PLL lock time? It really costs lots of time.
The other question is, if I simulate PSS for a divider, which takes a VerilogA frequency source as its freq input, theorically, the output freq is stable, so can I set "tstab" to a small value or just leave it blank?
Yes, trans noise is convenient to get, but I think it has little relationship with Phase Noise, right?
Thank you~