IvoryDesigner
Junior Member
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Posts: 10
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Hi,
I using a cmos 180nm technology. I have a digital buffer that have 20 mA peak, 0,6 mA average ans 3.8 mA rms.
So I have a general question about which current to use to check the minimum number of via, as the documentation of the design kit give only Jmax (maximum DC current density).
I know the saver way it to consider the maximum, but for density intergration I can't afford it unless it is a must!
Thank you to enlighten me about that point and to share your experience about routing constraint to deal with high AC current.
Regards,
KC
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