Hi, all.

   I am designing an 10dB BPF. But I find the phase margin of the OP is good at point A but poor at point B.
   If  this BPF is stable?

I think it is stable ? But not very sure.

Hello,
Where did you break the loop?? How did you find Phase margin. Use STB for better results.

Thanks,
Raj.

Thank you ,very much.

Using STB, get the phasemargin is 35. Is that result OK?

Hi,
it looks like your stability test OK. (As long as the input capacitor exists in the schematic for real. it Yes so you have good PM.
Cadence allow you to use STB simulation which do it for you.

Erez

kane wrote on Jan 8^th, 2013, 9:52pm:


From your Open Loop AC signal ( called OL(s) )
Create a formula in your calculator: CL(s) = OL(s) / ( 1+OL(s) ) and probe the amplitude in dB20 of this complex expression. If you see any overshoot somewhere, you can consider your circuit is not robustly stable, and if you see a significant peaking you can consider it is unstable.
Then add the phase of CL(s): if you see the amplitude decrease while phase increases, it means you have complex poles with positive real part: it means your loop is totally unstable.

Now the question is: what do you mean by "is it stable?"
a 35deg phase margin circuit is stable "mathematically speaking" because it will converge at t=infinity, but will have lots of ringing.

In all cases, the best test to do is to perform a transient simulation with a step stimuli on the input.