BackerShu
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Thanks loose-electron!
Actually, I am trying to check the design in a paper. [1] D. Dalton, et al., “A 12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE Journal of Solid State Circuit, vol. 40, no. 12, pp. 2713–2725, 2005.
A figure of the CDR block diagram is shown in the attachment (DPLL.jpg). By using the D/PLL structure proposed in this paper, Jitter Transfer (JTRAN) and Jitter Tolerance (JTOL) are decoupled while using a Phase Shifter in the feed-forward path. This Phase Shifter block is exactly the magic delay stage I am talking about, which needs to provide approximately 2UIpp delay at all data rate (from 12.5Mb/s to 2.7Gb/s) to achieve good JTOL performance.
The paper didn't talk much about the circuit design of this Phase Shitfer; and the only description is shown in the attachment (PSH.jpg). Based on the description, the delay (or RC time constant) of the Phase Shifter is adjusted according to data rate. I am not sure how they control the RC time constant exactly. Even if it can be implemented this way, I still feel difficult to control the delay range of the delay line to be 2UIpp for all the data rate range.
In addition, using differential cells to implement delay is very power consuming (power for this paper is 235mA@3.3V). I guess the paper employed the differential cells because of ISI requirement.
Still, I am thinking whether there are some other ways to implement this phase shifter more power efficiently, either in Analog CDR structure like this paper, or in Digital CDR structure meaning phase detector is replaced by bang-bang phase detector and loop filter is replaced by accumulator. Yes, input data is still NRZ data, which is analog in nature.
Any suggestions? (Just came to know that I can only post one attachment at a time. So the description for the Phase Shifter (magic delay stage) in the paper (PSH.jpg) is posted next. Sorry for inconvenience. )
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