Hello All,

I guess this has been discussed before, but could not find it, so decided to ask it here.

Is there a way we can extract board parasitics from Altium schematic/layout (preferably layout) in some format (like Cadence Spectre, spice, verlogA etc.) so that it can be used for chip level simulations using Cadence Spectre (or AMS)?

I have come to know that Cadence does support this if the layout was done in Cadence Allegro, but we are stuck with Altium.

If anybody can share some docs/pdfs on this flow will be much appreciated.

Thanks,
Rajdeep

Hi Raj,

Thanks for the reply. Our board designs are done in Altium only. So looking for a way of back annotation that starts from Altium layout/schematic.

Thanks
Rajdeep