Dear Pictou,
   yes in theory it can oscillate but why don't you follow some traditional crystal oscillator design like colpitts or some other std VCO?i didn't understand "what steps should I follow to design a circuit that will match the Barkhausen criteria". Up to my knowledge make sure that you have >1 gain at 40Mhz and enough phase, try to check through AC sim.
     What do you mean by the amplifier was used in its bandwidth. Normally amplifier will contribute some phase in excess to it's dc phase, for example take 3 stage ring vco in addition to 180 deg phase each contribute 60deg at the oscillation frequency. I guess in your case amplifier is providing 40deg in-excess and rest of the 120 deg by Cristal tank at the frequency of oscillation.
   What do you want to validate, to make sure it is oscillating normal transient analysis or PSS will be sufficient. If you want check noise performance use P-noise.

Thanks,
Raj.

 

Your schematic is peculiar in a few ways.  I've never seen a pierce oscillator with so many biases and even two stages!  An oscillator generally is large signal, so you'll be swamping out the biases of the extra transistors.  Start with a simple inverting stage.

You talk about Loop Gain (Barkhausen), but your schematic neither shows a Feedback Resistor, nor a model of the crystal.  Without either, you won't be able to simulate Loop gain or phase.

You would be able to simulate Neg R, and I encourage you to do so.
However, that is small signal, and you will be dealing with a larger signal in reality.

Good Luck,
WAVE

SMLogan -

NegR is basically an AC simulation.  Related to Gm*Rout.  Small signal.  
Transient is completely different analysis.  I agree it should also be performed, for large signal behavior.  
There is a direct correlation of startup results with Neg R and Transient, but don't combine or confuse the two.  In fact, there simulation test benches are necessarily different.

Sounds like we are both confused with his biasing.  
Yes, the traditional large R is for biasing.  
Plus, there can be significant interplay between it's size and other parasitic elements, that affect NegR and startup!  That is not obvious nor documented many places.

Wave

Hello everyone and thank you very much for your answers!

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@raja.cedt

I'm trying to design a Pierce oscillator, however in all the schematic I found, the schematic wasn't transistor level.
I didn't use a regular inverter because I couldn't control the output voltage levels.
I have several constraints about my input voltage level and ouput voltage level. I must use 5V supply voltage on transistors that can hold only 3.3V and my output level must be 1.2V. (However you couldn't know that, I forgot to mention it, I'm sorry).

About the Barkhausen criteria, actually my testbench was wrong so I thought that I didn't match the Barkhausen criteria, but now with proper simulation configuration I'm following the criteria.


I've been on this design for a month now. From all the publications and books I read, the amplifier inverter was always shifting the phase by 180° (therefore the inverter amplifier was in its bandwidth). I was so doubtful about my work that I started to question everything in my design. My superior told me that the design oscillator should take something like 2 weeks, and I'm stuck on it for 1 month already so I was quite panicked.

Yes the Pnoise is my next step, I mean... as soon as my oscillator works fine and I know why.

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@smlogan, thank you for helping me again

http://web.mit.edu/klund/www/weblatex/node4.html
okay, my world if falling apart... Well I prefer negative resistance anyway.

Quote:

Thank you very much I tried to find the meaning of the negative resistance for a while, thanks to you I finally have it.


I'll try to get these texts and tutorials, so I can fully understand what I'm doing.

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@wave

Yes you are right, I removed the follower stage (as I didn't need to adapt the impedance anyway). I couldn't use an inverter amplifier because I have to control the output voltage levels.

I had to use the numerous bias, because of another issue. I'm using 5V supply voltage on 3.3V transistors, I have to "lower" the voltage on some transistors so they won't be overstressed (but I haven't taken care of this problem yet).
And I'm sorry I forgot to draw the parallel resistance but it's present.

My new schematic :
http://www.pdfhost.net/index.php?Action=Download&File=14f34384d8c3b7aac18e8950f4...

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Thank you all again for your help. My simulations are now working, I'm oscillating, PSS does converge (but I will have to increase the accuracy).




However I have another problem. The drive level of the crystal model is only 100uW and I'm consuming up to 1069uW. I saw in a publication that to solve this, you need to add a resistor between the amplifier output and the crystal input.
Will this addition change all my previous calculations?

Thank you again.

Hello logan,

Very interesting article, there were a lot of information I haven't seen in any other article.

So if I understand correctly, the way presented to lower the power dissipation in the crystal is to change the load capacitance that the crystal sees. This way we shift the oscillation frequency a little in order to avoid the peak power consumption.

I tried this method but I had other issues, such as :

With the load capacitance specified by the crystal manufacturer (14pF) I have a swing of 2.5V for an oscillation frequency of 40.03056 MHz.
With 7pF, my swing is now 3.6V and at 40.0326 MHz.

However it seems that you didn't have this problem as in your table, the tab nammed limiting voltage remains the same. I think that my oscillator is too basic to use your technique as the power reduction is lowered because I have no voltage control on my output.

With 7pF load capacitance instead of 14pF, I went from a power consumption of 1069uW to 866uW. I used the same relation used when we are in resonnance as the phase shift is not that big, I think it's "okay" for a first estimation of the power consumption change. So it's definitely a reduction!
But it's not enough. Do you know how to reduce the amplitude of the oscillation?


Second issue is that I would like to lower my power dissipation by a factor 10 (going from 1069uW to 90uW), do you think that it's possible with changing the values of the load capacitor?

Thank you.

EDIT : Power dissipated is not 1069uW but 1455uW... it's even worse than I thought.

EDIT 2 : being stuck on your method, I tried to add a resistor, but I really don't know how it is supposed to lower the drive level...

Hello,
Yeah I forgot that I could ask the manufacturer to give me another load capacitance... forgot again....

Hmm, the method I'm using is the following :
(And yes, I just realized that I forgot to put RMS value instead of max)


P = R1 * I² = R1 * (V * 2pi * f * C2)².

My mistakes were that my Voltage was wrong, I forgot to get the RMS value and I took the swing instead of the amplitude. And I took C2 instead of C0.

For "V"oltage I understand my mistake, but are you sure that I must use C0 and not C2?

I'll check my math and the methodoly, thank you very much for your help!

Weird, In your article it says P = V²/R. I just assumed that the frequency parameter in the rest of the relation in the article was almost equal to 1 as I'm not really far from serie resonance, is it wrong?

I'll use the full relation.


EDIT : I'm just wondering something, to use this relation my signal needs to be a sinus right?
The shape of my signal is really bad :
http://www.hostingpics.net/viewer.php?id=859141oscillatorsaturation.png

In order to calculate the power dissipation, I think I need to make my signal a sinus first, what do you think?


EDIT 2 :
I tried reducing the ampitude of the output oscillations, my first thought was to reduce the gain and increase the load capacitance. It did decrease the oscillation but my DC gets lower and is too close to the ground. I'm still saturating on the bottom curve of the sinus.
Do know a way to control the oscillations?