Hi all,

Ironically enough I have inherited a few custom digital cells that use inherited connections for the supply pins.

I have modeled most of my design sub-blocks in Verilog-A for Spectre-Verilog sims, except for these custom cells as they don't have any supply pins.

For a simple inverter, I have tried using the usual, but I can't get the supply pins to extract for my Verilog-A code (the schematics extract just fine):

Here is the partial code as I don't have access to the full code right now:

// Inherited Supply Connections
// *************************
 electrical (* integer inh_conn_prop_name = "VPOS";
          integer inh_conn_def_value = "cds_globals.\\VPOS! "; *) vdd;

electrical (* integer inh_conn_prop_name = "VNEG";
          integer inh_conn_def_value = "cds_globals.\\VNEG! "; *) vss;

electrical (* integer inh_conn_prop_name = "VSUB";
         integer inh_conn_def_value = "cds_globals.\\VSUB! "; *) Vsub;

I'll appreciate any feedback & help with this.

Thanks,

Irfan

Irfan,

The model does not have supply pins in the classcial sense. The (IMO) easiest way to use with an analog design flow is to either change the schematic to inherited connections or the model to have supply pins.

- B O E

Irfan,
I assume your design (schematic) uses inherited connections as it does not have supply pins. In this case you use the inherited connection code you gave in your initial post (changing the names appropriately).
Then you can access the supplies with the signal names vdd, vss and Vsub (for your code fragment).
- B O E
PS (added): You can use either method for the supply - as long as schematic, model, ... of a cell all use the same one.

The attachments!