Hi Folks! :)
Maybe this post more suitable for Digital Design, but anyway i'm try...
I'm new in design of Delay Locked Loop, and i already have schematic solution .
After simulation i see some strange behavior, which i can not a explain...
First of all, criterion of lock DLL (startup time) is absence of pulses (pulses are generated by PD), these pulses 'tells' to CP in which direction needs to realign VCDL. But on low frequences (some corners) i see that both pulses are presented in end-of-simulation and NO trend to decreasing one of them..What is it? Autooscillations of DLL? How to explain this problem and to solve...To solve I tried to increase capacitor in CP circuit, anyway it blindest solution...
On high frequences i see absence one of pulses, is good, but another pulse no disappear, he decreased to final amplitude. I think that is no problem, if propose, what she is smaller than treshold of transistor, and CP doesn't work with this amplitude.
I some disapointed
![Sad Sad](https://designers-guide.org/forum/Templates/Forum/default/sad.gif)
, may all of this artefact of transients simulation, but precision is highest... May be is my misunderstanding in optimal parameters of CP pull up/pull down current, CP capacitor , frequency ranges of DLL.
Thanks for help!