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digital output keeps 0 in spectreverilog simulation (Read 3021 times)
ahhfyz
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Posts: 5
digital output keeps 0 in spectreverilog simulation
May 11
th
, 2013, 6:51am
Hi! I have used spectreverilog simulator before. Today I simulate a mixed-signal circuit again. The analog part works well, but all the digital output keeps "0". How does this happen? What should I do ?Thank you!
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boe
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Posts: 615
Re: digital output keeps 0 in spectreverilog simulation
Reply #1 -
May 14
th
, 2013, 6:38am
ahhfyz,
probably there is something wrong with the IEs (power supply, thresholds, ...).
- B O E
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