Kevin Aylward
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Matching is worse in subthreshold, although model accuracy is also a problem. Set up test current mirror and differential pair simulation, although the results are basically the same. Put a 10mv dc source in the gate or source of one of the transistors and see what the ratio difference in currents is when the current is swept. Spot numbers for a standard 220n/180n process gets ~25% mismatch for Vgst=-150mv to 8% mismatch for Vgst=+100 mv, falling to 2% mismatch at Vgst=+0.5V. Why? Well, 10 mv added on to 1/2V is a lot less than 10 mv added on to 100 mv, so mismatch goes approximately as Verror/Vgst, until it gets down to Vgst=0, where the approximation collapses, as the idealised approximation says that below threshold, current is zero! The exponential nature in subthreshold results in approximately a constant error ratio over much of the range. For general cmos design, keep Vgst above 100mv worse case, especially for current mirrors. Various performance parameters fall off below that value, although, sometimes 20 mv or so above zero Vgst may be ok. Noting that increasing W as an attempt to increase gm results in ever diminishing returns as Vgst gets below around 50mv, with a corresponding larger proportionate penalty in capacitance. Subthreshold is used because preventing subthreshold at very low currents requires very large gate lengths, which slow the system down even more that operating in subthreshold itself does. If the option is available, a bipolar is usually better for low currents, its gm is always higher, at any current.
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