ic_engr
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Hello Folks,
I have a verilog model. I generated a symbol for it and the IO Pins look fine. I woudl like to use this symbol (verilog behind) along wiht other analog schematics in order to perform LVS using Calibre.
I am wondering if the Clibre can generate the proper spice netlist from this verilog symbol.
Alternatively, I used v2lvs command from Calibre and generated a spice netlist. However, I would like to have the netlist as one of the views in the virtuoso ...
Any suggestions ?
Regards Abdullah
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