Dear aaron,
1. Most of the ring oscillators were controlled through tail current of differential pair or tri-state inverter bias current,i guess this is very similar to your case(of course you have a specific v2i rather than inherent ).

2. i didn't understand why v2i converter doesn't benefit from filtering, if you look at the transfer function from control node to pll output it  will be band pass function, so only around loop BW only noise appears at the output.        

3. I have seen Few design's which has active circuits between control node  and VCO,mostly they are level shift circuits.

Thanks,
Raj.                                                                              

Aaron,

The ring oscillator VCOs I have seen are tuned by controlling differential pair tail currents as you described.  I normally work with VCO noise referenced to the VCO output (instead of the control node), and when inserted into the PLL loop the noise transfer function is 1/(1+LG) which is indeed high pass.  

With that being said, I think it makes sense that the V2I conversion causes a jitter increase outside the loop bandwidth and reducing the KVCO should help.  Increasing the Kphi parameter could be done to return the loop bandwidth to its original value.  I am not sure what flexibility you have in this design but it may be possible to increase the loop bandwidth at the expense of in band jitter and reference spurs.  Again, I do not know what other performance constraints you are up against.

Hope this helps.

Tim

Aaron,

I would certainly not recommend increasing the loop bandwidth if it is already 1/10 of the reference frequency.  Theoretically it can be done but you need to analyze the loop as a sampled system which is much more complicated.  You probably already know, but all PLL loops are technically sampled systems and if you keep the loop bandwidth low enough compared to the reference frequency you can cheat and analyze the loop as a continuous time system.  If you are interested there are good references written by Jim Crawford at www.am1.us.  He has written text books and papers on the subject of analyzing PLLs as sampled systems.

Tim

did you do an E2E noise analysis of just the V to I converter and optimize that for noise?

Hi all,


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thanks, but yeah that's the first thing I tried. I found that the current I needed would make the V-I converter more power hungry than the VCO itself. And not only that, the current would have to actually be divided down before the noise from the V-I converter was no longer dominant. I'm now trying out using varactors instead of the fancy V-I converter. It seems the noise is better.

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well I just looked at the noise summary from the pnoise analysis in spectre and tried to minimize the largest contributors. But I guess its not fool proof because the noise summary seems to plot output noise and not phase noise.


thanks,
Aaron

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Actually for some reason I was thinking that the 1 MHz spot noise from the noise summary was literally at 1 MHz instead of 1 MHz from the carrier. But your tip has lead me to a better understanding, so thanks.

Aaron