Hai
i generated verilog code from model writer function in cadence and created symbol for that.

i used this symbol to create the test bench for ADC the problem is in my code i defined output as dout as a 8 bit register but when i created the test bench and netlist it is taking individual bits so i am getting error in simulation can any one help me how to simulate this in virtuoso ADE

in my symbol i have only bus pin