Chuck
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Posts: 6
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Hey guys,
I was reading a tutorial published by TI, and it was about continuous time delta sigma (DS) ADCs. Author wanted to compare discrete versus continuous time DS ADCs, and he said "in discrete time delta sigma ADC , unlike continuous time, the internal amplifiers must settle within some target resolution each period." No doubt that continuous time delta sigma has higher speed but lower resolution compared to discrete time, but I am not still clear about the part he claimed "amplifiers must settle within some target resolution". They should settle, but is there any target resolution for settling? I thought as long as they settle, it doesn't matter since it won't introduce any non linear error. Aside from that, since delta sigma ADCs are high resolution converters, say more than 18 bits, does it mean in each period amplifier should settle within this range: Vref/2^N ? where Vref is reference voltage of the ADC, and N is the resolution of the entire converter.
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