Hi All,

I have a question related to Delta Sigma ADC. I am using an OSR of 64 for a 1st order modulator. However,the input signal (sine wave of amplitude 0.5 to 4V @ 200kHz) is being sampled with a very less number of 1s, leading to a very low SNR value. (Negative!!)
Please let me know why I have such a less number of 1s in my output signal. I am using a switched capacitor design for the modulator.
Please see the attachment.
The red signal is the input sine wave.
The blue is the output of the 1-bit DAC which is fed back to the switch.

Thanks!

Regards,
ksnf3000

Hi avlsi,

Yes your right. I have used real circuits -transistor level design for 0.35 µm AMS technology. I have used ideal in MATLAB/Simulink and it works fine. I have checked my integrator and comparator also. Seems some issue with my integrator getting saturated. However,do you think this may be the reason for limited number of samples?

Thanks!!

Hi Raphael,

No.it still persists. My input frequency is around 1 kHz. In which calculation have you changed?

My spectrum is according to the NTF. The problem is my opamp (integrator) is getting saturated quickly, thats why it is not able to resolve further values,as you can see in the constant and large number of 1's in the figure when the sine curve is about to change.

Any ideas on this?

Regards,
Kashif