Hi all,

I am new to this group.

I wanted to understand the thermal noise behavior of MOS in triode region for oscillator design.

If we say that thermal noise of MOS is '4KTγ*gm';  γ varies with region of operation.

I did not find what is nominal γ in linear region. (Design of Analog CMOS Integrated Circuits - Behzad Razavi says in its 2012 reprint "theoretical determination of γ is under research")

I did simulations and found out that product of "γ*gm" increases as one moves to triode region. This product will determine noise current.

My question is "whether the γ is modeled correctly in recent simulators and my finding is correct"

Thank you...

Hi Raj..

I applied ideal current source at the drain of NMOS. The source was grounded. By varying gate voltage, I can control the region of operation.

The voltage noise at drain will be 4*K*T*γ*gm/(gds)^2
Simulator can give me drain noise voltage from which I can determine γ.

Is this method correct?

Thanks..

Hi Raj,

Sorry for late reply.

You are right! While modeling of MOS; it is said that it depends on 4*K*T*Gds0. Gds0 is the conductance when Vds is zero. This is nothing but gm in saturation. And γ we use as an empirical parameter.  Correct me if I wrong.

I simulated in spectre and observed that thermal noise current increases when MOS goes in triode region. The increase in noise is more when channel length is short.

The following image shows test schematic.  I kept Vgs constant and varied Vds. I am using CCCS to copy current and measure noise voltage across resistor which is in series with dependent current source.