I am studying PA from the paper "Design of 2.1GHz RF CMOS Power Amplifier for 3G" And I will simulate it in Cadence.
The paper use a single-ended two-stage Class AB PA in TSMC 0.25μm CMOS process. Here is one thing that I am confused. Please help.

Hi,

I guess most likely L3 is very large and doesn't affect the matching. If you include L3 in the matching, then it would be a pi network, and bandwidth would be degraded compared to an L-match.

regards,
Aaron

Hi,


If we use C and L3 for the match we get a step-up network, and if we use C and L4 we get a step down network.

To get good efficiency and linearity, you want the swing at the drain of M1 to be large, and the swing at the gate of M0 to be small. Hence you need a step-down network. However, bear in mind that this comes at the cost of gain.

I think that ideally L3 should be chosen to be large enough so as to have little effect on the matching. Practically, however, it depends how it is implemented. If it is on-chip, it may not be very large, and you might want to chose it to resonate with Cgg of M0, or simply to be part of the PI network. You could also consider using a transformer step-down network, but depending on the Q and impedance ratio, it may end up being more lossy.

L4 and C can then be chosen to get whatever impedance ratio you want. That depends on all kinds of factors...

regards,
Aaron

Hi,


Quote:


LC networks consist of only reactive devices. Hence they do not dissipate energy (ideally).

P_in = V_in²/R_in = P_out = V_out²/R_load

So from the above equation you can see that any increase in the impedance is accompanied by an increase in the voltage and vice versa.

Quote:


I think most texts on PAs will cover this. Basically power is dissipated in a device when there is simultaneously a voltage across the device and a current flowing through the device. For a MOSFET, the current and drain voltage waveforms are out-of-phase (for a real load), so if the signal is very large, the voltage waveform will reach a minimum when the current waveform reaches a maximum. If the voltage minimum can be made to be zero, then no energy is dissipated in the device at that point of time. Ideally in a switching PA, the MOSFET is completely ON for half of the time and completely OFF for half of the time. It acts like a switch. When completely ON, the current is maximum, but the drain voltage should be zero to ensure no power dissipation in the device. When completely OFF, the voltage can swing high, but the current flowing through the device should be zero.

Note that because in a switching PA the device is switched completely ON or OFF, the amplitude information in the signal is lost. So such amplifiers can't normally be used to amplify signals with amplitude modulation. There are of course ways around this, but this also kind of exposes the basic tradeoff between efficiency and linearity.

Quote:


It really depends on how you implement your inductor. If you are implementing it on-chip, you probably have a good case. From my experience (which may or may not really apply in your case), if you are implementing it on chip, transformers are a good choice. But then if your requirements are very relaxed, it might not matter.

One of the most important points which I don't think you revealed in your previous message is the required output power. This will be a big factor in your design. For high power designs, you will quickly find that every little trace of metal counts and has to be modeled using an EM simulator. It will also be very important to carefully design and optimize your matching networks. You may even need to chose an architecture whose main benefit is to relax the requirements on the device modeling.


regards,
Aaron