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Design for Testability for non-logic circuits (Read 2835 times)
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Taiwan
Design for Testability for non-logic circuits
Sep 22nd, 2013, 12:53am
 
Hi everyone,
DFT enables to identify the exact failure location in logic circuit. Just want to know if there exist similar concept for Analog/RF circuits.
If chip doesn't work on fabrication, how does one debug which block of it not working? May be one can have pads for direct-probing at i/p & o/p of each block. But then need to isolate the preceding & following stages. What are the built-in self testing techniques for Analog/RF.
Comments welcomed....Resources for detail reading appreciated
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