Designer’s Guide Community

Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.

Jul 24^th, 2024, 12:24am

‹ Previous topic | Next topic ›

Pages: 1

SNDR in Current Steering DAC (Read 7303 times)

lvbq

New Member

Offline

Posts: 8
Shanghai

SNDR in Current Steering DAC
Oct 08^th, 2013, 6:01am

Hi all ,

Resently I have simulated the SNDR of a 12b Current sterring DAC ,but it is only 54dB, thus the enob is 9bit . Simulation by Cadence without mc model.

So, I'm very confused why the DAC's SNDR was so bad ?

Can anyone give me some help?

By the way, How to tradoff the transistors' size of current source for the Statics and Dynamic performance ?

IP Logged

harpoon Senior Member Offline Posts: 112 Hampshire	Re: SNDR in Current Steering DAC Reply #1 - Oct 8^th, 2013, 6:20am usually down to mismatch. can you share some schematics and simulation plots ?
Back to top	IP Logged

lvbq New Member Offline Posts: 8 Shanghai	Re: SNDR in Current Steering DAC Reply #2 - Oct 8^th, 2013, 8:44am It's Current steerining DAC .the decoder is 8bit MSB thermal and 4bit binary . cascode current source biased by Bandgap and V2I. So, Why SNDR was so bad even without mc model? Best regards!
Back to top	IP Logged

harpoon

Senior Member

Offline

Posts: 112
Hampshire

Re: SNDR in Current Steering DAC
Reply #3 - Oct 9^th, 2013, 1:16am

you have to be careful with drain voltages in a current steering DAC, esp for high res DACs. I am guessing the loading seen by the current mirrors are slightly different across the codes. I am guessing at some point, you cascodes are entering the linear region. Doesn't need MC to see that.

Could also be the mismatch between the 8bit and 4 bit sections ... check your switches.

Also, try replacing components in yr design with ideal ones to identify the issue.

I'm afraid that is the best we can do without schematics and test benches ...

good luck (you'll need it ... suggest you think about layout as well !)

IP Logged

lvbq New Member Offline Posts: 8 Shanghai	Re: SNDR in Current Steering DAC Reply #4 - Oct 9^th, 2013, 8:41am Thanks。
Back to top	IP Logged

harpoon Senior Member Offline Posts: 112 Hampshire	Re: SNDR in Current Steering DAC Reply #5 - Oct 10^th, 2013, 3:41am hi lvbq, if you do manage to get to the bottom of it, it would be good to know what it was and how you fixed it ... all the best !
Back to top	IP Logged

lvbq

New Member

Offline

Posts: 8
Shanghai

Re: SNDR in Current Steering DAC
Reply #6 - Oct 10^th, 2013, 7:22am

harpoon wrote on Oct 10^th, 2013, 3:41am:

hi lvbq,

if you do manage to get to the bottom of it, it would be good to know what it was and how you fixed it ...

all the best !

Just from pre-simulation without mismatch model，I found that the Large CS transistor�s size can down the SFDR .

I think the dynamic impendance of the cascode current source becoming very low in high frequency（in Nyquist frequency）。

Therefore，There is a tradoff of the size of the current source （Is that called the tradoff between Static and Dynamic performance？）

My English just so so...I'm not a native speaker..I don't know whether you can understand what i mean。

IP Logged

harpoon Senior Member Offline Posts: 112 Hampshire	Re: SNDR in Current Steering DAC Reply #7 - Oct 11^th, 2013, 1:36am I am not sure I understand your email, but that's ok. Sounds like a sizing issue with your transistors. I am surprised that you are getting speed issues with your cascodes, but then again, you'll be the better judge. General rule of thumb ... size current mirrors to have a gm/I of ~10.
Back to top	IP Logged

lvbq

New Member

Offline

Posts: 8
Shanghai

Re: SNDR in Current Steering DAC
Reply #8 - Oct 11^th, 2013, 6:44am

harpoon wrote on Oct 11^th, 2013, 1:36am:

I am not sure I understand your email, but that's ok. Sounds like a sizing issue with your transistors.

I am surprised that you are getting speed issues with your cascodes, but then again, you'll be the better judge.

General rule of thumb ... size current mirrors to have a gm/I of ~10.

gm/I ~10 that's means vdsat=0.2 ?
But the variation of I ~1/vdsat ,therefore ,large vdsat can minimize the variation.

IP Logged

harpoon Senior Member Offline Posts: 112 Hampshire	Re: SNDR in Current Steering DAC Reply #9 - Oct 11^th, 2013, 7:25am just a rule of thumb ... try hunting down the following doc for more details. �Scalable GM/I Based MOSFET Model� Proc. Int. Semicond. Device Research Symp., pp. 615-618, Charlottesville, VA, December 10-13, 1997 it is the basis of the EKV modelling a while back ...
Back to top	IP Logged

Pages: 1

‹ Previous topic | Next topic ›