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The Designer's Guide Community Forum › Design › Mixed-Signal Design › Modeling Jitter in PLL-based Frequency Synthesizers
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Modeling Jitter in PLL-based Frequency Synthesizers (Read 1387 times)
mustangyhz
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china
Modeling Jitter in PLL-based Frequency Synthesizers
Oct 15th, 2013, 2:17am  
Does anybody download "Modeling Jitter in PLL-based Frequency Synthesizers" from www.designers-guide.org and test it in cadence?
How to simulate it? can you send me the project in cadence? thanks!
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