Hi All ,

During sinusoidal steady state TM line analysis ,
When Zs = Z0 , and Zo not equal to Zl then we have standing wave. Consider the case when there is a mismatch between source impedance Zs and Zo (intrinsic impedence) and also mismatch between Z0 and ZL (load impedence). I am not able to visualize the standing wave in this case. As per my thinking there will be a reflected wave at the source as well as the load . In this case I am not able to visualize the standing wave  because there are so many back and forth reflections  :-/
Please help me clear my understanding

Thanks raja for the reply.
I am aware of lattice dig. However , its time domain analysis. I am looking for steady state sinusoidal analysis. Many books don't deal with reflection from source while doing steady state sinusoidal analysis.Hence, i was curious and not clear about it.