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aaron_do

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Pipelined ADC without front-end SHA
Oct 31^st, 2013, 2:40am

Hi all,

I've noticed that a lot of pipelined ADCs don't have a front-end SHA. I figure that the reason is because nowadays most pipelined ADCs seem to use a digital error correction architecture which is insensitive to the sub-ADC's comparator threshold.

My questions are.

1. What implication does this have to kT/C noise? Obviously noise will be injected in the first stage, but will it be "error corrected" in subsequent stages?

2. Is it theoretically possible to remove the SHA from all of the subsequent stages too?

Any thoughts are welcome.

thanks,
Aaron

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sheldon

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Re: Pipelined ADC without front-end SHA
Reply #1 - Nov 8^th, 2013, 5:57am

Aaron,

� The following stages don't have explicit Sample and Holds. They
have gain stages. The implication on kTC noise is that without the
sampling capacitor the noise floor will be lower, since the S/H
occurs before any gain, that is, the S/H kTC noise is not attenuated.
Since pipeline ADC have used what you call digital error correction
since they first became available, I don't think that there is a relationship
between no S/H and error correction.

For the subsequent stages removing the capacitors means
using resistive gain stages which increases current and
results is more loading, less gain from the amplifiers. Do
you really want to burn more power and degrade the gain
of the stages?

Sheldon

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aaron_do

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Re: Pipelined ADC without front-end SHA
Reply #2 - Nov 18^th, 2013, 1:12am

Hi Sheldon,

thanks for the reply.

The following stages typically use an MDAC. If I understand the theory correctly, the MDAC is basically a S/H, plus an amplifier, plus a DAC. Therefore the caps need to be sized for kT/C noise just like an S/H. So although its not explicit, the operation is there.

Quote:

The implication on kTC noise is that without the sampling capacitor the noise floor will be lower, since the S/H occurs before any gain, that is, the S/H kTC noise is not attenuated.

Thanks. I think I understand it better now.

Quote:

I don't think that there is a relationship between no S/H and error correction.

I'm new to mixed-signal, so sorry if I'm on the wrong track here, but I believe there is a relationship. In a typical ADC (not pipelined), a S/H is necessary before any conversion since otherwise the ADC would be sensitive to timing errors. However, for a pipelined ADC, the digital error correction relaxes the requirement on the sub-ADCs such that timing errors ultimately don't show up at the output. Therefore, without error correction, you would need to add the S/H. Feel free to correct me.

Quote:

For the subsequent stages removing the capacitors means using resistive gain stages which increases current and results is more loading, less gain from the amplifiers.

Yes that's true assuming there isn't a different way to get the 2x gain.

Aaron

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there is no energy in matter other than that received from the environment - Nikola Tesla

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carlgrace

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Berkeley, CA

Re: Pipelined ADC without front-end SHA
Reply #3 - Dec 25^th, 2013, 9:01pm

aaron_do wrote on Oct 31^st, 2013, 2:40am:

Hi all,

I've noticed that a lot of pipelined ADCs don't have a front-end SHA. I figure that the reason is because nowadays most pipelined ADCs seem to use a digital error correction architecture which is insensitive to the sub-ADC's comparator threshold.

My questions are.

1. What implication does this have to kT/C noise? Obviously noise will be injected in the first stage, but will it be "error corrected" in subsequent stages?

2. Is it theoretically possible to remove the SHA from all of the subsequent stages too?

Any thoughts are welcome.

thanks,
Aaron

I disagree a bit with Sheldon's reply here. �First, each stage most certainly does have an S/H, otherwise it would be impossible for each stage to operate on a different input sample. �It is the per-stage S/H amplifiers that make a Pipelined ADC unique rather than a "ripple through" ADC that used to be popular in Bipolar technology or the Two-step CMOS ADC. �Second, resistive gain stages are typically much lower power than switched-cap gain stages because they can run open loop. �The problem with resistive gain stages is they are very nonlinear (no feedback to linearize them) so they need complex calibration in practice.

To answer your questions:

1. �Typically input S/H adds noise because it is a noise source without adding gain. �This means the first pipeline stage supplies the same amount of input referred noise with or without the input S/H. �Typically the noise specification is set by system-level considerations and a designer will use the lower overall noise by lowering the capacitance of the 1st stage (which increases its noise but lowers its power).

2. �I don't think it is possible to remove the S/H in the different stages because how else could the different stages operate on different samples at the same time? �You could in theory imagine an asynchronous ripple ADC but it is not very practical for general use.

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